FIG. 9 is a cross-sectional view of an island region using a RESURF structure of high withstand-voltage in a conventional high withstand-voltage semiconductor device. FIG. 9(a) is a sectional view and FIG. 9(b) is a plan view of the structure. FIG. 9(a) shows the sectional structure taken along the dashed line of FIG. 9(b).
In FIG. 9, reference numeral 1 indicates a p−-type semiconductor substrate. Reference numeral 2 indicates an n-type well. Reference numeral 4 indicates an n−-type well. Reference numeral 5 indicates a p-type island formed on the surface of the n-type well 2, which serves as a back gate region of an nchMOS transistor.
The n−-type well 4 is used to obtain a high withstand voltage. When a high voltage is applied to the n-type well 2, the n−-type well 4 is virtually depleted so as to relax a surface electric field. This is a technique generally known as a RESURF operation (see, for example, U.S. Pat. No. 4,292,642 as to a RESURF structure).
When a high potential island region is formed in such a construction, the following problems arise.
A first problem is that if then-type well 2 is not formed much deeper, then a depletion layer extending from the p−-type semiconductor substrate 1 reaches the p-type island 5 to thereby produce punch-through, whereby the entire withstand voltage is limited by the punch-through.
A second problem is that when an element or device such as a vertical npn-Tr, a vertical nch-DMOS or the like, using the n-type well 2 itself as an electrode is formed in the n-type well 2, the resistance of a portion equivalent to the n-type well 2 becomes large and hence device characteristics deteriorate.
FIG. 10 shows an example in which the vertical npn-Tr is formed in the n-type well 2 shown in FIG. 9. FIG. 10(a) is a cross-sectional view of the example and shows a cross-section taken along the dashed line of the plan view of FIG. 10(b). Thus, when the n-type well 2 itself is used as the electrode, the resistance of a portion equivalent to the n-type well 2 is large and hence device characteristics encounter deterioration.
A third problem is as follows. A method is known in which an island region is partially divided into portions when the above-described BipTr is incorporated into the structure, and a region therebetween of the p−-type semiconductor substrate 1 is depleted to thereby ensure separation between elements or devices. However, the surface of the p−-type semiconductor substrate 1 is generally low in impurity concentration. Leakage is apt to occur due to n-type reversal, and when a reverse-preventive diffused region is added to the surface to prevent reversal, reduction occurs in island withstand voltage due to the added diffused region.
FIG. 11 shows an example in which the island region shown in FIG. 9 is divided into n-type wells 2a and 2b and a reverse-preventive p-type diffused region 7 is formed in the surface of a p−-type semiconductor substrate 1 developed between the divided n-type wells 2a and 2b. FIG. 11(a) is a cross-sectional view of the example and illustrates a cross section taken along the dashed line of the plan view shown in FIG. 11(b). Even in this structure, island withstand-voltage might be reduced in reverse.